The Research Accelerator for Multiple Processors (RAMP) is an affordable and versatile multiprocessor emulation platform being built as a large collaborative effort. RAMP hardware, from processors to coherent caches to networks, is implemented in field-programmable gate arrays (FPGAs) for flexibility, accuracy, visibility, cost and performance. It is designed to be composable, where different components can be quickly written, assembled and run. By using hardware rather than simulation, RAMP is fast enough to run real codes and be useful to software. By using conventional instruction set architectures and providing peripheral support required by operating systems, RAMP runs full, unmodified software stacks. RAMP's intended audience includes anyone designing and using multiprocessor systems, including architect researchers, software developers, and end users. In this talk, I will describe the background and current state of the RAMP platform development and related projects using the underlying FPGA platform.
Scaling of silicon integrated technology into the deep sub-100 nm space brings with it a number of formidable challenges to the designer. Issues such as design complexity, power dissipation, process variability and reliability are challenging the traditional design methodologies. In this presentation, it is conjectured that the only viable long-term solution to these challenges is to drastically revise the way we do design, and a roadmap of potential solutions is presented. Massively parallel, error-resilient architectures potentially combined with new models of computation and communication are on the horizon. Ultimately, these innovative design solutions will help to pave the way to the post-silicon era. The presentation will be illustrated with examples of research performed at the GigaScale Systems Research Center (GSRC).